DFT 2006 - Call for Papers

CALL FOR PAPERS

Overview

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.

The Symposium will be held in Arlington/Washington DC, USA, at the Hilton Arlington & Towers Hotel. The hotel is located in the upscale Ballston area of Arlington, Virginia and is linked by skybridge to the Ballston Common Mall and NSF Office Complex. The Ballston neighborhood provides close proximity to high-tech engineering firms and government research offices.

The topics include (but are not limited to) the following ones:

Yield Analysis, Modeling and Enhancement
Defect/Fault analysis and models; statistical yield modeling; critical area and other metrics.
Repair, Restructuring and Reconfiguration
Repairable logic, fault-isolation, reconfiguration, and repair; restructurable and reconfigurable circuit design; on-line reconfiguration and repair.
Testing Techniques
Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits.
Error Detection, Correction, and Recovery
Self-testing and self-checking design; error-control coding; fault masking logic design; recovery scheme using space/time redundancy.
Defect and Fault Tolerance
Reliable circuit synthesis; radiation hardened/tolerant processes and design; transient/soft faults (SEU) tolerance, delay defect/fault tolerance.
Dependability Analysis and Validation
Fault injection techniques and environments; dependability characterization of IC and systems.
Emerging Technologies
Defect and fault tolerance in Carbon Nanotubes, Quantum-dot Cellular Automata, Quantum Computing, and Single Electron Transistors.
Safety Critical Systems
Design for defect and fault tolerance in safety critical systems and applications such as: automotive, railway, avionics, industrial control, and space.

Author Information

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Prospective authors should prepare an extended summary or the full paper (up to 9 pages in the IEEE 6X9 format), to be submitted as PDF file. Uncompressed unencapsulated postscript may also be used when necessary. Submission will be electronically only. Use the contact author's last name as file name; add numerals in the case of multiple submissions (e.g., lo1, lo2). Detailed information about the submission process will be made available on the symposium web page:

http://netgroup.uniroma2.it/DFT06/

Authors should notify their submission to the Program Chairs by e¬mail, indicating the title, authors’ names, affiliation, mail address, phone, fax and e¬mail and the name of the contact author. The submission should also indicate the intended presenter. We are also interested in panel sessions that involve industrial experiences: please send an email to the Program Chairs with a brief description (1 page maximum) of the panel discussion you would like to propose.

Prospective authors should adhere to the following deadlines:

Submission deadline: May 31, 2006
Notification of acceptance: June 30, 2006
Camera ready full papers: July 31, 2006

The proceedings will be published by the IEEE Computer Society. Authors will have the opportunity to submit extended versions of the papers published at the symposium in a special issue of a journal. For general information, contact the General co-Chairs. For paper submission information, contact the Program co-Chairs.

Committees

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General co-Chairs

Nohpill Park
Oklahoma State University, USA
Phone: +1 405 744 7937
Fax: +1 408 734 5050
E-mail: npark@cs.okstate.edu

Hideo Ito
Chiba University, JAPAN
Phone: +81 43 290 3253
Fax: +81 43 290 3269
E-mail: h.ito@faculty.chiba-u.jp

Program co-Chairs

Adelio Salsano
University of Rome “Tor Vergata”
Phone: +39 06 7259 7340
Fax: +39 06 202519
E-mail: salsano@ing.uniroma2.it

Nur Touba
University of Texas at Austin, USA
Phone: +1 512 232 1456
Fax: +1 512 471 5532
E-mail: touba@ece.utexas.edu

Local Arrangement Chair

Mohammad. Tehranipoor
UMBC Baltimore, USA
E-mail: tehrani@umbc.edu

Publicity Chair

Marco Ottavi
Northeastern University, USA
E-mail: mottavi@ece.neu.edu

Program Committee

Rob Aitken, ARM, USA
Lorena Anghel, TIMA labs, FRANCE
Cristiana Bolchini, Politec. di Milano, ITALY
Glenn Chapman, Simon Fraser U., CANADA
Minsu Choi, U. of Missouri-Rolla, USA
Dirk DeVries, Phillips, FRANCE
Eiji Fujiwara, Tokyo Inst. of Tech., JAPAN
Dimitris Gizopoulos, U. of Piraeus, GREECE
Ismed Hartanto, Agilent Technologies, USA
Susumu Horiguchi, JAIST, JAPAN
Chih-Tsun Huang, Nat'l Tsing Hua U., TAIWAN
Hideo Ito, Chiba U., JAPAN
Vijay Jain, U. of South Florida, USA
Yong-Bin Kim, Northeastern U., USA
Israel Koren, UMASS Amherst, USA
Regis Leveugle, TIMA labs, FRANCE
Jien-Chung Lo, U. of Rhode Island, USA
Fabrizio Lombardi, Northeastern U., USA
Martin Margala, U. of Rochester, USA
Cecilia Metra, U. of Bologna, ITALY
Jackie Meyer, Wichita State U., USA
Nohpill Park, Oklahoma State U., USA
Sule Ozev, Duke U., USA
Zebo Peng, Linkoping U., SWEDEN
Vincenzo Piuri, U. of Milan, ITALY
Witold Pleskacz, Warsaw U.T., POLAND
Irith Pomeranz, Purdue U., USA
Maurizio Rebaudengo, Politec. di Torino, ITALY
Sudhakar Reddy, U. of Iowa, USA
Donatella Sciuto, Politec. di Milano, ITALY
Renato Stefanelli, Politec. di Milano, ITALY
XiaoLing Sun, U. of Alberta, CANADA
Claude Thibeault, Ecole de Tech., CANADA
Nobuo Tsuda, NTT, JAPAN
Raoul Velazco, TIMA labs, FRANCE
Srikanth Venkataraman, Intel, USA
Moritoshi Yasunaga, Tsukuba U. JAPAN

For more information, visit us on the web at: http://netgroup.uniroma2.it/DFT06/

The 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Fault-Tolerant Computing Technical Committee and Test Technology Technical Council (TTTC).

CALL FOR PAPERS
Overview -- Author Information
Overview
DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest. The Symposium will be held in Arlington/Washington DC, USA, at the Hilton Arlington & Towers Hotel. The hotel is located in the upscale Ballston area of Arlington, Virginia and is linked by skybridge to the Ballston Common Mall and NSF Office Complex. The Ballston neighborhood provides close proximity to high-tech engineering firms and government research offices. The topics include (but are not limited to) the following ones: Yield Analysis, Modeling and Enhancement Defect/Fault analysis and models; statistical yield modeling; critical area and other metrics. Repair, Restructuring and Reconfiguration Repairable logic, fault-isolation, reconfiguration, and repair; restructurable and reconfigurable circuit design; on-line reconfiguration and repair. Testing Techniques Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits. Error Detection, Correction, and Recovery Self-testing and self-checking design; error-control coding; fault masking logic design; recovery scheme using space/time redundancy. Defect and Fault Tolerance Reliable circuit synthesis; radiation hardened/tolerant processes and design; transient/soft faults (SEU) tolerance, delay defect/fault tolerance. Dependability Analysis and Validation Fault injection techniques and environments; dependability characterization of IC and systems. Emerging Technologies Defect and fault tolerance in Carbon Nanotubes, Quantum-dot Cellular Automata, Quantum Computing, and Single Electron Transistors. Safety Critical Systems Design for defect and fault tolerance in safety critical systems and applications such as: automotive, railway, avionics, industrial control, and space.
Author Information	top
Prospective authors should prepare an extended summary or the full paper (up to 9 pages in the IEEE 6X9 format), to be submitted as PDF file. Uncompressed unencapsulated postscript may also be used when necessary. Submission will be electronically only. Use the contact author's last name as file name; add numerals in the case of multiple submissions (e.g., lo1, lo2). Detailed information about the submission process will be made available on the symposium web page: http://netgroup.uniroma2.it/DFT06/ Authors should notify their submission to the Program Chairs by e¬mail, indicating the title, authors’ names, affiliation, mail address, phone, fax and e¬mail and the name of the contact author. The submission should also indicate the intended presenter. We are also interested in panel sessions that involve industrial experiences: please send an email to the Program Chairs with a brief description (1 page maximum) of the panel discussion you would like to propose. Prospective authors should adhere to the following deadlines: Submission deadline: May 31, 2006 Notification of acceptance: June 30, 2006 Camera ready full papers: July 31, 2006 The proceedings will be published by the IEEE Computer Society. Authors will have the opportunity to submit extended versions of the papers published at the symposium in a special issue of a journal. For general information, contact the General co-Chairs. For paper submission information, contact the Program co-Chairs.
Committees	top
General co-Chairs Nohpill Park Oklahoma State University, USA Phone: +1 405 744 7937 Fax: +1 408 734 5050 E-mail: npark@cs.okstate.edu Hideo Ito Chiba University, JAPAN Phone: +81 43 290 3253 Fax: +81 43 290 3269 E-mail: h.ito@faculty.chiba-u.jp Program co-Chairs Adelio Salsano University of Rome “Tor Vergata” Phone: +39 06 7259 7340 Fax: +39 06 202519 E-mail: salsano@ing.uniroma2.it Nur Touba University of Texas at Austin, USA Phone: +1 512 232 1456 Fax: +1 512 471 5532 E-mail: touba@ece.utexas.edu Local Arrangement Chair Mohammad. Tehranipoor UMBC Baltimore, USA E-mail: tehrani@umbc.edu Publicity Chair Marco Ottavi Northeastern University, USA E-mail: mottavi@ece.neu.edu Program Committee Rob Aitken, ARM, USA Lorena Anghel, TIMA labs, FRANCE Cristiana Bolchini, Politec. di Milano, ITALY Glenn Chapman, Simon Fraser U., CANADA Minsu Choi, U. of Missouri-Rolla, USA Dirk DeVries, Phillips, FRANCE Eiji Fujiwara, Tokyo Inst. of Tech., JAPAN Dimitris Gizopoulos, U. of Piraeus, GREECE Ismed Hartanto, Agilent Technologies, USA Susumu Horiguchi, JAIST, JAPAN Chih-Tsun Huang, Nat'l Tsing Hua U., TAIWAN Hideo Ito, Chiba U., JAPAN Vijay Jain, U. of South Florida, USA Yong-Bin Kim, Northeastern U., USA Israel Koren, UMASS Amherst, USA Regis Leveugle, TIMA labs, FRANCE Jien-Chung Lo, U. of Rhode Island, USA Fabrizio Lombardi, Northeastern U., USA Martin Margala, U. of Rochester, USA Cecilia Metra, U. of Bologna, ITALY Jackie Meyer, Wichita State U., USA Nohpill Park, Oklahoma State U., USA Sule Ozev, Duke U., USA Zebo Peng, Linkoping U., SWEDEN Vincenzo Piuri, U. of Milan, ITALY Witold Pleskacz, Warsaw U.T., POLAND Irith Pomeranz, Purdue U., USA Maurizio Rebaudengo, Politec. di Torino, ITALY Sudhakar Reddy, U. of Iowa, USA Donatella Sciuto, Politec. di Milano, ITALY Renato Stefanelli, Politec. di Milano, ITALY XiaoLing Sun, U. of Alberta, CANADA Claude Thibeault, Ecole de Tech., CANADA Nobuo Tsuda, NTT, JAPAN Raoul Velazco, TIMA labs, FRANCE Srikanth Venkataraman, Intel, USA Moritoshi Yasunaga, Tsukuba U. JAPAN
For more information, visit us on the web at: http://netgroup.uniroma2.it/DFT06/
The 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Fault-Tolerant Computing Technical Committee and Test Technology Technical Council (TTTC).